Memory arrays with hierarchical or “segmented” bitline architecture have been developed in recent years in order to increase the integration density of memory chips. This architecture allows for a reduced number of space-consuming sense amplifiers for a given number of memory cells, thus reducing chip size or increasing memory capacity for a given sized chip.
In a hierarchical bitline architecture, each column within a memory cell array includes a number of equal length local bitlines (LBLs), directly connected to the memory cells, and to global bitlines (GBLs), for example, composed of a high conductivity metal disposed at a higher fabrication layer than the local bitlines. By way of example, each local bitline may connect to several hundred memory cells, while each global bitline is connected directly to a sense amplifier and is selectively coupled to a number of local bitlines in a common column by a number of switches. To access (e.g., write) a memory cell connected to a particular local bitline, the switch connecting that local bitline to the global bitline is closed, while the other switches in the column are open.
In order to write a standard six-transistor memory cell, two actions are required. The candidate memory cell's wordline must be raised and a differential voltage (typically full rail) must be applied to the cell's bitline. The particular wordline that is raised is determined by the write_address signal. Typically, the memory cells in a word address space share a common bitline pair. In a hierarchical bitline design, however, the bitline pairs are partitioned into “local” segments that correspond to subsets of the word address space. When writing a memory cell in this hierarchical configuration, it is sufficient to simply apply the same differential to each local bitline segment. This method, however, is inefficient from a power dissipation perspective.
Therefore, there exists a need in the art for a technique for generating control signals which can be used to control the writing of individual subarray bitline segments in a memory array configured with multiple memory subarrays, such as a static random access memory (SRAM) array configured with a hierarchical bitline architecture.